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ltc3814-5 1 38145fc 60v current mode synchronous step-up controller the ltc3814-5 is a synchronous step-up switching regu- lator controller that can generate output voltages up to 60v. the ltc3814-5 uses a constant off-time peak current control architecture to deliver very high duty cycles with accurate cycle-by-cycle current limit without requiring a sense resistor. a precise internal reference provides 0.5% dc accuracy. a high bandwidth (25mhz) error ampli? er provides very fast line and load transient response. large 1 gate driv- ers allow the ltc3814-5 to drive large power mosfets for higher current applications. the operating frequency is selected by an external resistor and is compensated for variations in v in . a shutdown pin allows the ltc3814-5 to be turned off reducing the supply current to < 230a. n 24v fan supplies n 48v telecom and base station power supplies n networking equipment, servers n automotive and industrial control systems n high output voltages: up to 60v n large 1 gate drivers n no current sense resistor required n dual n-channel mosfet synchronous drive n 0.5% 0.8v voltage reference n fast transient response n programmable soft-start n generates 5.5v driver supply n power good output voltage monitor n adjustable off-time/frequency: t off(min) < 100ns n adjustable cycle-by-cycle current limit n undervoltage lockout on driver supply n output overvoltage protection n thermally enhanced 16-pin tssop package high ef? ciency high voltage step-up converter ef? ciency vs load current features description applications typical application pgood v off pgood v rng i th v fb sgnd run/ss i off 1000pf 0.01f 100pf v in 4.5v to 14v 22f v out 24v 4a v out 100k 100k 263k ltc3814-5 extv cc tg sw bg pgnd intv cc ndrv boost 38145 ta01 0.1f m1 si7848dp m2 si7848dp 1f 29.4k 1k 270f 2 4.7h + + d1 mbr1100 load (a) 0 efficiency (%) 90 95 4 85 80 1 2 3 100 38145 ta01b v in = 12v v in = 5v l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611.
ltc3814-5 2 38145fc supply voltages intv cc ................................................... C0.3v to 14v (intv cc C pgnd), (boost C sw) ......... C0.3v to 14v boost (continuous) ............................. C0.3v to 85v boost (400ms) .................................. C0.3v to 95v extv cc .................................................. C0.3v to 15v (extv cc C intv cc ) .................................. C12v to 12v (ndrv C intv cc ) voltage ........................... C0.3v to 10v sw voltage (continuous) .............................. C1v to 70v sw voltage (400ms) ..................................... C1v to 80v i off voltage (continuous) .......................... C0.3v to 70v i off voltage (400ms) ................................. C0.3v to 80v run/ss voltage ........................................... C0.3v to 5v pgood voltage ............................................ C0.3v to 7v v rng , v off voltages ................................... C0.3v to 14v fb voltage ................................................. C0.3v to 2.7v tg, bg, intv cc , extv cc rms currents .................50ma operating junction temperature range (notes 2, 3, 7) ....................................... C40c to 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 i off v off v rng pgood i th v fb run/ss sgnd boost tg sw pgnd bg intv cc extv cc ndrv 17 t jmax = 125c, ja = 38c/w exposed pad (pin 17) is gnd, must be soldered to pcb absolute maximum ratings package/order information lead free finish tape and reel part marking package description temperature range ltc3814efe-5#pbf ltc3814efe-5#trpbf 3814efe-5 16-lead plastic tssop C40c to 125c ltc3814ife-5#pbf ltc3814ife-5#trpbf 3814ife-5 16-lead plastic tssop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ order information
ltc3814-5 3 38145fc symbol parameter conditions min typ max units main control loop intv cc intv cc supply voltage l 4.35 14 v i q intv cc supply current intv cc shutdown current run/ss > 1.5v (notes 4, 5) run/ss = 0v 3 224 6 600 ma a i boost boost supply current run/ss > 1.5v (note 5) run/ss = 0v 240 0 400 5 a a v fb feedback voltage (note 4) 0c to 85c C40c to 85c C40c to 125c l l l 0.796 0.794 0.792 0.792 0.800 0.800 0.800 0.800 0.804 0.806 0.806 0.808 v v v v ?v fb,line feedback voltage line regulation 5v < intv cc < 14v (note 4) l 0.002 0.02 %/v v sense(max) maximum current sense threshold v rng = 2v, v fb = 0.76v v rng = 0v, v fb = 0.76v v rng = intv cc , v fb = 0.76v 256 70 170 320 95 215 384 120 260 mv mv mv v sense(min) minimum current sense threshold v rng = 2v, v fb = 0.84v v rng = 0v, v fb = 0.84v v rng = intv cc , v fb = 0.84v C300 C85 C200 mv mv mv i vfb feedback current v fb = 0.8v 20 150 na a vol (ea) error ampli? er dc open-loop gain 65 100 db f u error amp unity gain crossover frequency (note 6) 25 mhz v run/ss shutdown threshold 0.6 0.9 1.2 v i run/ss run/ss source current run/ss = 0v 0.7 1.4 2.5 a v vccuv intv cc undervoltage lockout intv cc rising hysteresis l 4.05 4.2 0.5 4.35 v v oscillator t off off-time i off = 100a i off = 300a 1.55 515 1.85 605 2.15 695 s ns t off(min) minimum off-time i off = 2000a 100 ns t on(min) minimum on-time 350 ns driver i bg,peak bg driver peak source current v bg = 0v 0.7 1 a r bg,sink bg driver pulldown r ds(on) 1 1.5 i tg,peak tg driver peak source current v tg C v sw = 0v 0.7 1 a r tg,sink tg driver pulldown r ds(on) 1 1.5 pgood output ?v fbov pgood upper threshold pgood lower threshold v fb rising v fb falling 7.5 C7.5 10 C10 12.5 C12.5 % % ?v fb,hyst pgood hysteresis v fb returning 1.5 3 % v pgood pgood low voltage i pgood = 5ma 0.3 0.6 v i pgood pgood leakage current v pgood = 5v 0 2 a the l denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c (note 2), intv cc = v boost = v rng = v extvcc = v ndrv = v off = 5v, unless otherwise speci? ed. electrical characteristics
ltc3814-5 4 38145fc note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3814-5 is tested under pulsed load conditions such that t j t a . the ltc3814e-5 is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3814i-5 is guaranteed to meet performance speci? cations over the full C40c to 125c operating junction temperature range. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc3814-5: t j = t a + (p d ? 38c/w) symbol parameter conditions min typ max units pg delay pgood delay v fb falling 125 s v cc regulators v extvcc extv cc switchover voltage extv cc rising extv cc hysteresis l 4.5 0.1 4.7 0.25 0.4 v v v intvcc,1 intv cc voltage from extv cc 6v < v extvcc < 15v 5.2 5.5 5.8 v ?v extvcc,1 v extvcc - v intvcc at dropout i cc = 20ma, v extvcc = 5v 75 150 mv ?v loadreg,1 intv cc load regulation from extv cc i cc = 0ma to 20ma, v extvcc = 10v 0.01 % v intvcc,2 intv cc voltage from ndrv regulator linear regulator in operation 5.2 5.5 5.8 v ?v loadreg,2 intv cc load regulation from ndrv i cc = 0ma to 20ma, v extvcc = 0 0.01 % i ndrv current into ndrv pin v ndrv C v intvcc = 3v 20 40 60 a v ccsr maximum supply voltage trickle charger shunt regulator 15 v i ccsr maximum current into ndrv/intv cc trickle charger shunt regulator, intv cc 16.7v (note 8) 10 ma note 4: the ltc3814-5 is tested in a feedback loop that servos v fb to the reference voltage with the i th pin forced to a voltage between 1v and 2v. note 5: the dynamic input supply current is higher due to the power mosfet gate charging being delivered at the switching frequency (q g ? f sw ). note 6: guaranteed by design. not subject to test. note 7: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 8: i cc is the sum of current into ndrv and intv cc . overcurrent operation the l denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c (note 2), intv cc = v boost = v rng = v extvcc = v ndrv = v off = 5v, unless otherwise speci? ed. electrical characteristics typical performance characteristics load transient response start-up v out 200mv/div 100s/div front page circuit v in = 12v 0a to 4a load step 38145 g01 i out 2a/div v out 10v/div 1ms/div front page circuit v in = 12v i load = 1a 38145 g02 run/ss 4v/div i l 5a/div v out 10v/div 200s/div front page circuit v in = 12v v rng = 1v r short = 1 38145 g03 i l 5a/div
ltc3814-5 5 38145fc ef? ciency vs load current frequency vs input voltage frequency vs load current i th voltage vs load current off-time vs i off current off-time vs temperature typical performance characteristics current sense threshold vs i th voltage maximum current sense threshold vs v rng voltage maximum current sense threshold vs temperature load (a) efficiency (%) 90 95 85 80 100 38145 g04 v in = 12v v in = 24v v in = 36v v out = 50v 04 123 5 input voltage (v) 5 frequency (khz) 260 280 300 13 240 220 200 7 9 11 15 38145 g05 i load = 0a i load = 1a front page circuit load current (a) 0 frequency (khz) 260 280 300 240 220 200 1 2 3 4 38145 g06 v in = 5v v in = 12v front page circuit load current (a) i th voltage (v) 1 2 0 3 38145 g07 front page circuit v in = 12v v rng = 1v 04 123 5 i th voltage (v) 0 C400 current sense threshold (mv) C200 C300 C100 0 100 200 400 0.5 1 1.5 2 38145 g08 2.5 3 300 v rng = 2v 1.4v 1v 0.7v 0.5v i off current (a) 10 10 off-time (ns) 100 1000 10000 100 1000 10000 38145 g09 v off = intv cc temperature (c) C50 off-time (ns) 640 660 680 25 75 38145 g10 620 600 C25 0 50 100 125 580 560 i off = 300a v rng voltage (v) 0.5 maximum current sense threshold (mv) 200 38145 g11 100 0 1 1.5 300 400 2 temperature (c) C50 C25 190 maximum current sense threshold (mv) 210 240 0 50 75 38145 g12 200 230 220 25 100 125 v rng = intv cc
ltc3814-5 6 38145fc typical performance characteristics reference voltage vs temperature driver pulldown r ds(on) vs temperature driver peak source current vs supply voltage driver pulldown r ds(on) vs supply voltage extv cc switch resistance vs temperature intv cc current vs temperature intv cc shutdown current vs temperature driver peak source current vs temperature temperature (c) C50 C25 0.797 reference voltage (v) 0.799 0.803 0.802 0 50 75 38145 g14 0.798 0.801 0.800 25 100 125 temperature (c) C50 0.5 peak source current (a) 1.0 1.5 C25 0 25 50 38145 g15 75 100 125 v boost = v intvcc = 5v temperature (c) C50 r ds(on) () 1.25 1.50 1.75 25 75 38145 g16 1.00 0.75 C25 0 50 100 125 0.50 0.25 v boost = v intvcc = 5v drv cc /boost voltage (v) 4 5 7 9 11 13 peak source current (a) 3.0 2.5 2.0 1.5 1.0 0.5 0 6 8 10 12 38145 g17 14 drv cc /boost voltage (v) 4 r ds(on) () 0.6 0.8 0.9 1.0 1.1 6 8 914 13 38145 g21 0.7 57 10 11 12 temperature (c) C50 4 5 7 25 75 38145 g19 3 2 C25 0 50 100 125 1 0 6 resistance () temperature (c) C50 C25 0 intv cc current (ma) 2 5 0 50 75 38145 g20 1 4 3 25 100 125 intv cc = 5v temperature (c) C50 intv cc current (a) 25 38145 g21 200 100 C25 0 50 0 400 300 75 100 125 intv cc = 5v
ltc3814-5 7 38145fc typical performance characteristics intv cc current vs intv cc voltage intv cc shutdown current vs intv cc voltage run/ss pull-up current vs temperature shutdown threshold vs temperature intv cc voltage (v) 0 2.0 2.5 3.5 610 38145 g22 1.5 1.0 24 81214 0.5 0 3.0 intv cc current (ma) intv cc voltage (v) 0 200 250 350 610 38145 g23 150 100 24 81214 50 0 300 intv cc current (a) temperature (c) C50 ss/track current (a) 2 3 25 75 38145 g24 1 C25 0 50 100 125 0 run/ss = 0v temperature (c) C50 shutdown threshold (v) 2.0 25 38145 g25 1.4 1.0 C25 0 50 0.8 0.6 2.2 1.8 1.6 1.2 75 100 125
ltc3814-5 8 38145fc i off (pin 1): off-time current input. tie a resistor from v out to this pin to set the one-shot timer current and thereby set the switching frequency. v off (pin 2): off-time voltage input. voltage trip point for the on-time comparator. tying this pin to an external resistive divider from the input makes the off-time pro- portional to v in . the comparator defaults to 0.7v when the pin is grounded and defaults to 2.4v when the pin is connected to intv cc . v rng (pin 3): sense voltage limit set. the voltage at this pin sets the nominal sense voltage at maximum output current and can be set from 0.5v to 2v by a resistive divider from intv cc . the nominal sense voltage defaults to 95mv when this pin is tied to ground, and 215mv when tied to intv cc . pgood (pin 4): power good output. open-drain logic output that is pulled to ground when the output voltage is not between 10% of the regulation point. the output voltage must be out of regulation for at least 125s before the power good output is pulled to ground. i th (pin 5): error ampli? er compensation point and cur- rent control threshold. the current comparator threshold increases with control voltage. the voltage ranges from 0v to 2.6v with 1.2v corresponding to zero sense voltage (zero current). v fb (pin 6): feedback input. connect v fb through a resistor divider network to v out to set the output voltage. run/ss (pin 7): run/soft-start input. for soft-start, a capacitor to ground at this pin sets the ramp rate of the maximum current sense threshold. pulling this pin below 0.9v will shut down the ltc3814-5, turn off both of the external mosfet switches and reduce the quiescent sup- ply current to 224a. sgnd (pin 8): signal ground. all small-signal components should connect to this ground and eventually connect to pgnd at one point. ndrv (pin 9): drive output for external pass device of the linear regulator for intv cc . connect to the gate of an external nmos pass device and a pull-up resistor to the input voltage v in or the output voltage v out . extv cc (pin 10): external driver supply voltage. when this voltage exceeds 4.7v, an internal switch connects this pin to intv cc through an ldo and turns off the exter- nal mosfet connected to ndrv, so that controller and gate drive are drawn from extv cc . intv cc (pin 11): main supply and driver supply pin. all internal circuits and bottom gate output driver are powered from this pin. intv cc should be bypassed to sgnd and pgnd with a low esr (x5r or better) 1f capacitor in close proximity to the ltc3814-5. bg (pin 12): bottom gate drive. the bg pin drives the gate of the bottom n-channel main switch mosfet. this pin swings from pgnd to intv cc . pgnd (pin 13): bottom gate return. this pin connects to the source of the pull-down mosfet in the bg driver and is normally connected to ground. sw (pin 14): switch node connection to inductor and bootstrap capacitor. voltage swing at this pin is from a schottky diode (external) voltage drop below ground to v out . tg (pin 15): top gate drive. the tg pin drives the gate of the top n-channel synchronous switch mosfet. the tg driver draws power from the boost pin and returns to the sw pin, providing true ? oating drive to the top mosfet. boost (pin 16): top gate driver supply. the boost pin supplies power to the ? oating tg driver. boost should be bypassed to sw with a low esr (x5r or better) 0.1f capacitor. an additional fast recovery diode from intv cc to the boost pin will create a complete ? oating charge- pumped supply at boost. gnd (exposed pad pin 17): ground. the exposed pad must be soldered to pcb ground. pin functions
ltc3814-5 9 38145fc functional diagram C + 1.4v 1.4 a 0.7v r c c c1 c c2 v rng 3 i th C + C + v voff i ioff t off = (76pf) r sq 20k i cmp shdn switch logic bg intv cc on ov 0.9v 4v ea 0.8v 38145 fd sgnd r fb1 r fb2 8 6 run shdn fault 12 pgnd 13 pgood v fb sw 14 tg boost c b 15 16 intv cc ndrv 11 9 C + C + uv 0.72v ov 0.88v c vcc v out m2 m1 m3 l c out c in + d b 4 + + v in v in C + overtemp sense 5v reg intv cc i off 1 v out r off v off 2 C + intv cc uv C + C + off on 5.5v 4.7v 5.5v 4.2v 2.6v extv cc 10 5 0.8v ref C + run/ss 7 v in
ltc3814-5 10 38145fc operation figure 1. floating tg driver supply and negative bg return main control loop the ltc3814-5 is a current mode controller for dc/dc step-up converters. in normal operation, the top mosfet is turned on for a ? xed interval determined by a one-shot timer (ost). when the top mosfet is turned off, the bot- tom mosfet is turned on until the current comparator i cmp trips, restarting the one-shot timer and initiating the next cycle. inductor current is determined by sensing the voltage between the pgnd and sw pins using the bottom mosfet on-resistance. the voltage on the i th pin sets the comparator threshold corresponding to the inductor peak current. the fast 25mhz error ampli? er ea adjusts this voltage by comparing the feedback signal v fb to the internal 0.8v reference voltage. if the load current increases, it causes a drop in the feedback voltage relative to the reference. the i th voltage then rises until the average inductor current again matches the load current. the operating frequency is determined implicitly by the top mosfet on-time (t off ) and the duty cycle required to maintain regulation. the one-shot timer generates a top mosfet on-time that is inversely proportional to the i off current and proportional to the v off voltage. connecting v out to i off and v in to v off with a resistive divider keeps the frequency approximately constant with changes in v in . the nominal frequency can be adjusted with an external resistor r off . pulling the run/ss pin low forces the controller into its shutdown state, turning off both m1 and m2. forcing a voltage above 0.9v will turn on the device. fault monitoring/protection constant off-time current mode architecture provides ac- curate cycle-by-cycle current limit protectiona feature that is very important for protecting the high voltage power supply from output overcurrent conditions. the cycle-by-cycle current monitor guarantees that the induc- tor current will never exceed the value programmed on the v rng pin. overvoltage and undervoltage comparators ov and uv pull the pgood output low if the output feedback voltage exits a 10% window around the regulation point after the internal 125s power bad mask timer expires. furthermore, in an overvoltage condition, m2 is turned off and m1 is turned on immediately and held on until the overvoltage condition clears. the ltc3814-5 provides an undervoltage lockout com- parator for the intv cc supply. the intv cc uv threshold is 4.2v to guarantee that the mosfets have suf? cient gate drive voltage before turning on. if intv cc is under the uv threshold, the ltc3814-5 is shut down and the drivers are turned off. strong gate drivers the ltc3814-5 contains very low impedance drivers ca- pable of supplying amps of current to slew large mosfet gates quickly. this minimizes transition losses and allows paralleling mosfets for higher current applications. a 60v ? oating high side driver drives the topside mosfet and a low side driver drives the bottom side mosfet (see figure 1). the bottom side driver is supplied directly from the intv cc pin. the top mosfet drivers are biased from ? oating bootstrap capacitor c b , which normally is recharged during each off cycle through an external diode from intv cc when the top mosfet turns off. in an output overvoltage condition, where it is possible that the bot- tom mosfet will be off for an extended period of time, an internal timeout guarantees that the bottom mosfet is turned on at least once every 25s for one top mosfet on-time period to refresh the bootstrap capacitor. boost tg sw bg pgnd intv cc intv cc ltc3814-5 m2 + + v in c in v out c out d b c b 38145 f01 m1 l
ltc3814-5 11 38145fc the basic ltc3814-5 application circuit is shown on the ? rst page of this data sheet. external component selection is primarily determined by the maximum input voltage and load current and begins with the selection of the power mosfet switches. the ltc3814-5 uses the on-resistance of the synchronous power mosfet for determining the inductor current. the desired amount of ripple current and operating frequency largely determines the inductor value. next, c out is selected for its ability to handle the large rms current and is chosen with low enough esr to meet the output voltage ripple and transient speci? cation. finally, loop compensation components are selected to meet the required transient/phase margin speci? cations. duty cycle considerations for a boost converter, the duty cycle of the main switch is: d = 1? v in v out ;d max = 1? v in(min) v out the maximum v out capability of the ltc3814-5 is inversely proportional to the minimum desired operating frequency and minimum off-time: v out(max) = v in(min) f min ?t off(min) 60v maximum sense voltage and the v rng pin the control circuit in the ltc3814-5 measures the input current by using the r ds(on) of the bottom mosfet or by using a sense resistor in the bottom mosfet source, so the output current needs to be re? ected back to the operation input in order to dimension the power mosfet properly and to choose the maximum sense voltage. based on the fact that, ideally, the output power is equal to the input power, the maximum average input current and average inductor current is: i in(max) = i l,avg(max) = i o(max ) 1? d max the current mode control loop will not allow the induc- tor peak to exceed v sense(max) /r sense . in practice, one should allow some margin for variations in the ltc3814- 5 and external component values, and a good guide for selecting the maximum sense voltage when v ds sensing is used is: v sense(max) = 1.7 ? r ds(on) ?i o(max ) 1? d max v sense is set by the voltage applied to the v rng pin. once v sense is chosen, the required v rng voltage is calculated to be: v rng = 5.78 ? (v sense(max) + 0.026) an external resistive divider from intv cc can be used to set the voltage of the v rng pin between 0.5v and 2v resulting in nominal sense voltages of 60mv to 320mv. additionally, the v rng pin can be tied to sgnd or intv cc in which case the nominal sense voltage defaults to 95mv or 215mv, respectively. ic/driver supply power the ltc3814-5s internal control circuitry and top and bot- tom mosfet drivers operate from a supply voltage (intv cc pin) in the range of 4.5v to 14v. if the input supply voltage or another available supply is within this voltage range it can be used to supply ic/driver power. if a supply in this range is not available, two internal regulators are available to generate a 5.5v supply from the input or output. an internal low dropout regulator is good for voltages up to 15v, and the second, a linear regulator controller, controls the gate of an external nmos to generate the 5.5v supply. since the nmos is external, the user has the ? exibility to choose a bv dss as high as necessary. applications information
ltc3814-5 12 38145fc power mosfet selection the ltc3814-5 requires two external n-channel power mosfets, one for the bottom (main) switch and one for the top (synchronous) switch. important parameters for the power mosfets are the breakdown voltage bv dss , threshold voltage v (gs)th , on-resistance r ds(on) , miller capacitance and maximum current i ds(max) . since the bottom mosfet is used as the current sense element, particular attention must be paid to its on-resis- tance. mosfet on-resistance is typically speci? ed with a maximum value r ds(on)(max) at 25c. in this case, additional margin is required to accommodate the rise in mosfet on-resistance with temperature: r ds(on)(max) = r sense t the t term is a normalization factor (unity at 25c) accounting for the signi? cant variation in on-resistance with temperature (see figure 2) and typically varies from 0.4%/ c to 1.0%/ c depending on the particular mosfet used. ing its off-time and must be chosen with the appropriate breakdown speci? cation. the ltc3814-5 is designed to be used with a 4.5v to 14v gate drive supply (intv cc pin) for driving logic-level mosfets (v gs(min) 4.5v). for maximum ef? ciency, on-resistance r ds(on) and input capacitance should be minimized. low r ds(on) minimizes conduction losses and low input capacitance minimizes transition losses. mosfet input capacitance is a combi- nation of several components but can be taken from the typical gate charge curve included on most data sheets (figure 3). figure 2. r ds(on) vs temperature figure 3. gate charge characteristic the curve is generated by forcing a constant input cur- rent into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. the ? at portion of the curve is the result of the miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is ? at) is speci? ed for a given v ds drain voltage, but can be adjusted for different v ds voltages by multiplying by the ratio of the application v ds to the curve speci? ed v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated v ds voltage speci? ed. c miller is the most important se- lection criteria for determining the transition loss term in the top mosfet but is not directly speci? ed on mosfet data sheets. c rss and c os are speci? ed sometimes but de? nitions of these parameters are not included. the most important parameter in high voltage applications is breakdown voltage bv dss . both the top and bottom mosfets will see full output voltage plus any additional ringing on the switch node across its drain-to-source dur- junction temperature (c) C50 t normalized on-resistance 1.0 1.5 150 38145 f02 0.5 0 0 50 100 2.0 + C v ds v out v gs miller effect q in ab c miller = (q b C q a )/v ds v gs v + C 38145 f03 applications information
ltc3814-5 13 38145fc when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out ? v in v out synchronous switch duty cycle = v in v out the power dissipation for the main and synchronous mosfets at maximum output current are given by: p main = d max i o(max) 1 d max
2 ( t )r ds(on) + 1 2 v out 2 i o(max) 1 d max
(r dr )(c miller ) ? 1 intv cc ?v th(il) + 1 v th(il) (f) p sync = 1 1 d max
(i o(max) ) 2 ( t )r ds(0n) where t is the temperature dependency of r ds(on) , r dr is the effective top driver resistance (approximately 2 at v gs = v miller ). v th(il) is the data sheet speci? ed typical gate threshold voltage speci? ed in the power mosfet data sheet at the speci? ed drain current. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique described above. both mosfets have i 2 r losses while the bottom n-channel equation includes an additional term for transition losses. both top and bottom mosfet i 2 r losses are greatest at lowest v in , and the top mosfet i 2 r losses also peak during an overcurrent condition when it is on close to 100% of the period. for most ltc3814-5 applications, the transition loss and i 2 r loss terms in the bottom mosfet are comparable, so best ef? ciency is obtained by choosing a mosfet that optimizes both r ds(on) and c miller . since there is no transition loss term in the syn- chronous mosfet, however, optimal ef? ciency is obtained by minimizing r ds(on) by using larger mosfets or paralleling multiple mosfets. multiple mosfets can be used in parallel to lower r ds(on) and meet the current and thermal requirements if desired. the ltc3814-5 contains large low impedance drivers capable of driving large gate capacitances without signi? cantly slowing transition times. in fact, when driv- ing mosfets with very low gate charge, it is sometimes helpful to slow down the drivers by adding small gate resistors (10 or less) to reduce noise and emi caused by the fast transitions. operating frequency the choice of operating frequency is a tradeoff between ef? ciency and component size. low frequency operation improves ef? ciency by reducing mosfet switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. the operating frequency of ltc3814-5 applications is determined implicitly by the one-shot timer that controls the on-time t off of the synchronous mosfet switch. the on-time is set by the current into the i off pin and the voltage at the v off pin according to: t off = v voff i ioff 76pf () tying a resistor r off from v out to the i off pin yields a syn- chronous mosfet on-time inversely proportional to v out . this results in the following operating frequency and also keeps frequency constant as v out ramps up at start-up: f = v in v voff ?r off (76pf) (hz) the v off pin can be connected to intv cc or ground or can be connected to a resistive divider from v in . the v off pin has internal clamps that limit its input to the one-shot timer. if the pin is tied below 0.7v, the input to the one- shot is clamped at 0.7v. similarly, if the pin is tied above 2.4v, the input is clamped at 2.4v. note, however, that if the v off pin is connected to a constant voltage, the operating frequency will be proportional to the input voltage v in . figures 4a and 4b illustrate how r off relates to switching frequency as a function of the input voltage and v off voltage. to hold frequency constant for input applications information
ltc3814-5 14 38145fc voltage changes, tie the v off pin to a resistive divider from v in , as shown in figure 5. choose the resistor values so that the v rng voltage equals about 1.55v at the mid-point of v in as follows: v in,mid = v in(max) + v in(min) 2 = 1.55v ? 1 + r1 r2 with these resistor values, the frequency will remain relatively constant at: f = 1+ r1/ r2 r off (76pf) (hz) for the range of 0.45v in to 1.55 ? v in , and will be propor- tional to v in outside of this range. changes in the load current magnitude will also cause a frequency shift. parasitic resistance in the mosfet switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current increases. by shortening the off-time slightly as current increases, constant-frequency operation can be maintained. this is accomplished with a resistor connected from the i th pin to the i off pin to increase the i off current slightly as v ith increases. the values required will depend on the parasitic resistances in the speci? c application. a good starting point is to feed about 10% of the r off cur- rent with r ith as shown in figure 6. applications information figure 4a. switching frequency vs r off (v off = intv cc ) figure 4b. switching frequency vs r off (v off connected to a resistor divider from v in ) figure 6. correcting frequency shift with load current changes figure 5. v off connection to keep the operating frequency constant as the input supply varies r off (k) 10 100 switching frequency (khz) 1000 100 1000 38145 f04a v in = 5v v in = 24v v in = 12v r off (k) 10 100 switching frequency (khz) 1000 100 1000 38145 f04b 1+r1/r2 = 3.2 (v in , mid = 5v) 1+r1/r2 = 7.7 (v in , mid =12v) 1+r1/r2 = 15.5 (v in , mid = 24v) r2 r1 v in v off ltc3814-5 38145 f05 1000pf r off r ith v out i off i th ltc3814-5 38145 f06 10r off v out r ith =
ltc3814-5 15 38145fc minimum on-time and dropout operation the minimum on-time t on(min) is the smallest amount of time that the ltc3814-5 is capable of turning on the bottom mosfet, tripping the current comparator and turning the mosfet back off. this time is generally about 350ns. the minimum on-time limit imposes a minimum duty cycle of t on(min) /(t on(min) + t off ). if the minimum duty cycle is reached, due to a rising input voltage for example, then the output will rise out of regulation. the maximum input voltage to avoid dropout is: v in(max) = v out t off t on(min) + t off a plot of maximum duty cycle vs switching frequency is shown in figure 7. the required saturation of the inductor should be chosen to be greater than the peak inductor current: i l(sat) i o(max ) 1? d max + i l 2 once the value for l is known, the type of inductor must be selected. high ef? ciency conver ters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or kool m ? cores. a variety of inductors designed for high current, low voltage applications are available from manufacturers such as sumida, panasonic, coiltronics, coilcraft and toko. schottky diode d1 selection the schottky diode d1 shown in the front page schematic conducts during the dead time between the conduction of the power mosfet switches. it is intended to prevent the body diode of the synchronous mosfet from turning on and storing charge during the dead time, which can cause a modest (about 1%) ef? ciency loss. the diode can be rated for about one half to one ? fth of the full load current since it is on for only a fraction of the duty cycle. the peak reverse voltage that the diode must withstand is equal to the regulator output voltage. in order for the diode to be effective, the inductance between it and the synchronous mosfet must be as small as possible, mandating that these components be placed adjacently. the diode can be omitted if the ef? ciency loss is tolerable. output capacitor selection in a boost converter, the output capacitor requirements are demanding due to the fact that the current waveform is pulsed. the choice of component(s) is driven by the acceptable ripple voltage which is affected by the esr, esl and bulk capacitance as shown in figure 8e. the total output ripple voltage is: v out = i o(max) 1 f?c out + esr 1? d max where the ? rst term is due to the bulk capacitance and second term due to the esr. applications information figure 7. maximum switching frequency vs duty cycle inductor selection an inductor should be chosen that can carry the maximum input dc current which occurs at the minimum input volt- age. the peak-to-peak ripple current is set by the inductance and a good starting point is to choose a ripple current of at least 40% of its maximum value: i l = 40% ? i o(max ) 1? d max the required inductance can then be calculated to be: l = v in(min) ?d max f? i l 2.0 1.5 1.0 0.5 0 0 0.25 0.50 0.75 38145 f07 1.0 dropout region v in /v out switching frequency (mhz)
ltc3814-5 16 38145fc for many designs it is possible to choose a single capacitor type that satis? es both the esr and bulk c requirements for the design. in certain demanding applications, however, the ripple voltage can be improved signi? cantly by con- necting two or more types of capacitors in parallel. for example, using a low esr ceramic capacitor can minimize the esr step, while an electrolytic capacitor can be used to supply the required bulk c. once the output capacitor esr and bulk capacitance have been determined, the overall ripple voltage wave- form should be veri? ed on a dedicated pc board (see pc board layout checklist section for more information on component placement). lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look signi? cantly worse than they would be on a properly designed pc board. the output capacitor in a boost regulator experiences high rms ripple currents, as shown in figure 8d. the rms output capacitor ripple current is: i rms(cout) i o(max) ? v o ?v in(min) v in(min) note that the ripple current ratings from capacitor manu- facturers are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be placed in parallel to meet size or height requirements in the design. manufacturers such as nichicon, nippon chemi-con and sanyo should be considered for high performance throughhole capacitors. the os-con (organic semicon- ductor dielectric) capacitor available from sanyo has the lowest product of esr and size of any aluminum electrolytic at a somewhat higher price. an additional ceramic capaci- tor in parallel with os-con capacitors is recommended to reduce the effect of their lead inductance. in surface mount applications, multiple capacitors placed in parallel may be required to meet the esr, rms current handling and load step requirements. dry tantalum, special polymer and aluminum electrolytic capacitors are available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density applications information figure 8. switching waveforms for a boost converter than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. several excellent surge-tested choices are the avx tps and tpsv or the kemet t510 series. aluminum electrolytic capacitors have signi? cantly higher esr, but can be used in cost-driven applications providing that consideration is given to ripple current ratings and long term reliability. other capacitor types include panasonic sp and sanyo poscaps. in applications with v out > 30v, however, choices are limited to aluminum electrolytic and ceramic capacitors. v in ld sw 8a. circuit diagram 8b. inductor and input currents c out v out r l i in i l 8c. switch current i sw t on 8d. diode and output currents 8e. output voltage ripple waveform i o i d v out (ac) t off v esr ringing due to total inductance (board + cap) v cout 38145 f08
ltc3814-5 17 38145fc input capacitor selection the input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input and the input current waveform is continuous (see figure 8b). the input voltage source impedance determines the size of the input capacitor, which is typically in the range of 10f to 100f. a low esr capacitor is recommended though not as critical as for the output capacitor. the rms input capacitor ripple current for a boost con- verter is: i rms(cin) = 0.3 ? v in(min) l?f ?d max please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. be sure to specify surge-tested capacitors! output voltage the ltc3814-5 output voltage is set by a resistor divider according to the following formula: v out = 0.8v 1 + r fb1 r fb2 the external resistor divider is connected to the output as shown in the functional diagram, allowing remote voltage sensing. the resultant feedback signal is compared with the internal precision 800mv voltage reference by the error ampli? er. the internal reference has a guaranteed tolerance of less than 1 %. tolerance of the feedback resistors will add additional error to the output voltage. 0.1% to 1% resistors are recommended. top mosfet driver supply (c b , d b ) an external bootstrap capacitor c b connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from intv cc when the switch node is low. when the top mosfet turns on, the switch node rises to v out and the boost pin rises to approximately v out + intv cc . the boost capacitor needs to store about 100 times the gate charge required by the top mosfet. in most applications 0.1f to 0.47f, x5r or x7r dielectric capacitor is adequate. the reverse breakdown of the external diode, d b , must be greater than v out . another important consideration for the external diode is the reverse recovery and reverse leakage, either of which may cause excessive reverse current to ? ow at full reverse voltage. if the reverse current times reverse voltage exceeds the maximum al- lowable power dissipation, the diode may be damaged. for best results, use an ultrafast recovery diode such as the mmdl770t1. ic/mosfet driver supplies (intv cc ) the ltc3814-5 drivers and the ltc3814-5 internal circuits are supplied from the intv cc pin (see figure 1). these pins have an operating range between 4.2v and 14v. if the input voltage or another supply is not available in this voltage range, two internal regulators are provided to simplify the generation of this ic/driver supply voltage as described in the next sections. the n drv pin regulator the n drv pin controls the gate of an external nmos as shown in figure 9b and can be used to generate a regu- lated 5.5v supply from v in or v out . since the nmos is external, it can be chosen with a bv dss or power rating as high as necessary to safely derive power from a high voltage input or output voltage. in order to generate an intv cc supply that is always above the 4.2v uv threshold, the supply connected to the drain must be greater than 4.2v + r ndrv ? 40a + v t . the extv cc pin regulator a second low dropout regulator is available for voltages 15v. when a supply that is greater than 4.7v is con- nected to the extv cc pin, the internal ldo will regulate 5.5v on intv cc from the extv cc pin voltage and will also disable the ndrv pin regulator. this regulator is disabled when the ic is shut down, when intv cc < 4.2v, or when extv cc < 4.7v. applications information
ltc3814-5 18 38145fc using the intv cc regulators one, both or neither of these regulators can be used to generate the 5.5v ic/driver supply depending on the circuit requirements, available supplies, and the voltage range of v in or v out . deriving the 5.5v supply from v in is more ef? cient, however deriving it from v out has the advantage of maintaining regulation of v out when v in drops below the uv threshold. four possible con? gurations are shown in figures 9a through 9d, and are described as follows: 1. figure 9a. if the v in voltage or another low voltage supply between 4.5v and 14v is available, the sim- plest approach is to connect this supply directly to the intv cc and drv cc pins. the internal regulators are disabled by shorting ndrv and extv cc to intv cc . 2. figure 9b. if v in(max) > 14v, an external nmos con- nected to the ndrv pin can be used to generate 5.5v from v in . v in(min) must be > 4.5v + r ndrv ? 40a + v t to keep intv cc above the uv threshold and the bv dss of the external nmos must be chosen to be greater than v in(max) . the extv cc regulator is disabled by grounding the extv cc pin. 3. figure 9c. if the v in(max) < 14.7v and v in is allowed to fall below 4.2v without disrupting the boost converter operation, use this con? guration. the intv cc supply is derived from v in until the v out > 4.7v. once intv cc is derived from v out , v in can fall below the 4v uv threshold without losing regulation of v out . note that in this con? guration, v in must be > ~5v at least long enough to start up the ltc3814-5 and charge v out > 4.7v. also, since v out is connected to the extv cc pin, this con? guration is limited to v out < 15v. 4. figure 9d. similar to con? guration 3 except that v out is allowed to be >15v since v out is connected to an external nmos with appropriately rated bv dss . v in has same start-up requirement as 3. applications information figure 9. four possible ways to generate intv cc supply v out 15v (a) 4.2v to 14v supply available (b) intv cc from v in , v in > 14v (c) intv cc from v out , v out 15v (d) intv cc from v out , v out > 15v 38145 f09 ndrv extv cc intv cc + v in < 14.7v 5.5v ndrv extv cc intv cc ltc3814-5 v in 5.5v ndrv r ndrv extv cc intv cc + v out 5.5v r ndrv + ltc3814-5 ltc3814-5 + C 4.5v to 14v ndrv ext v cc intv cc + ltc3814-5 v in < 14.7v
ltc3814-5 19 38145fc power dissipation considerations applications using large mosfets and high frequency of operation may result in a large drv cc /intv cc supply current. therefore, when using the linear regulators, it is necessary to verify that the resulting power dissipation is within the maximum limits. the drv cc /intv cc supply current consists of the mosfet gate current plus the ltc3814-5 quiescent current: i cc = (f)(q g(top) + q g(bottom) ) + 3ma when using the internal ldo regulator, the power dissipa- tion is internal so the rise in junction temperature can be estimated from the equation given in note 2 of the electrical characteristics as follows: t j = t a + i extvcc ? (v extvcc C v intvcc )(38c/w) and must not exceed 125c. likewise, if the external nmos regulator is used, the worst case power dissipation is calculated to be: p mosfet = (v drain(max) C 5.5v) ? i cc and can be used to properly size the device. feedback loop/compensation introduction in a typical ltc3814-5 circuit, the feedback loop consists of two sections: the modulator/output stage and the feedback ampli? er/compensation network. the modulator/output stage consists of the current sense component and in- ternal current comparator, the power mosfet switches and drivers, and the output ? lter and load. the transfer function of the modulator/output stage for a boost con- verter consists of an output capacitor pole, r l c out , and an esr zero, r esr c out , and also a right-half plane zero, (r l / l)(v in 2 /v out 2 ). it has a gain/phase curve that is typi- cally like the curve shown in figure 10 and is expressed mathematically in the following equation. h(s) = v out (s) v ith (s) = r l ?v in ?v sense(max) 2.4 ? v out ?r ds(on) ? 1+ s?r esr ?c out 1+ s?r l ?c out ?1 s? l r l ? v out 2 v in 2 s = j2 f this portion of the power supply is pretty well out of the users control since the current sense is chosen based on maximum output load, and the output capacitor is usually chosen based on load regulation and ripple requirements without considering ac loop response. the feedback am- pli? er, on the other hand, gives us a handle on which to adjust the ac response. the goal is to have an 180 phase shift at dc so the loop regulates and less than 360 phase shift at the point where the loop gain falls below 0db, i.e., the crossover frequency, with as much gain as possible at frequencies below the crossover frequency. since the feedback ampli? er adds an additional 90 phase shift to the phase shift already present from the modulator/output stage, some phase boost is required at the crossover frequency to achieve good phase margin. the design procedure (described in more detail in the next section) is to (1) obtain a gain/phase plot of modulator/output stage, (2) choose a crossover frequency and the required phase boost, and (3) calculate the compensation network. applications information figure 10. bode plot of boost modulator/output stage (1) frequency (hz) gain (db) phase (deg) 38145 f10 00 C90 C180 90 180 gain phase
ltc3814-5 20 38145fc the two types of compensation networks, type 2 and type 3 are shown in figures 11 and 12. when component values are chosen properly, these networks provide a phase bump at the crossover frequency. type 2 uses a single pole-zero pair to provide up to about 60 of phase boost while type 3 uses two poles and two zeros to provide up to 150 of phase boost. the compensation of boost converters are complicated by two factors: the rhp zero and the dependence of the loop gain on the duty cycle. the rhp zero adds additional phase lag and gain. the phase lag degrades phase margin and the added gain keeps the gain high typically in the frequency region where the user is trying the roll off the gain below 0db. this often forces the user to choose a crossover frequency at a lower frequency than originally desired. the duty cycle effect of gain (see above transfer function) causes the phase margin and crossover frequency to be dependent on the input supply voltage which may cause problems if the input voltage varies over a wide range since the compensation network can only be optimized for a speci? c crossover frequency. these two factors usually can be overcome if the crossover frequency is chosen low enough. feedback component selection selecting the r and c values for a typical type 2 or type 3 loop is a nontrivial task. the applications shown in this data sheet show typical values, optimized for the power components shown. they should give acceptable performance with similar power components, but can be way off if even one major power component is changed signi? cantly. applications that require optimized transient response will require recalculation of the compensation values speci? cally for the circuit in question. the underly- ing mathematics are complex, but the component values can be calculated in a straightforward manner if we know the gain and phase of the modulator at the crossover frequency. modulator gain and phase can be obtained in one of three ways: measured directly from a breadboard, or if the appropriate parasitic values are known, simulated or generated from the modulator transfer function. mea- surement will give more accurate results, but simulation or transfer function can often get close enough to give a working system. to measure the modulator gain and phase directly, wire up a breadboard with an ltc3814-5 and the actual mosfets, inductor and input and output capacitors that the ? nal design will use. this breadboard should use appropriate construction techniques for high speed analog circuitry: bypass capacitors located close to the ltc3814-5, no long wires connecting components, appropriately sized ground returns, etc. wire the feedback ampli? er with a 0.1f feedback capacitor from i th to fb and a 10k to 100k resistor from v out to fb. choose the bias resistor (r b ) as required to set the desired output voltage. disconnect r b from ground and connect it to a signal generator or to the source output of a network analyzer to inject a test signal into the loop. measure the gain and phase from the i th pin to the output node at the positive terminal of the output capacitor. make sure the analyzers input is ac coupled so that the dc voltages present at both the i th and v out nodes dont corrupt the measurements or damage the analyzer. applications information figure 11. type 2 schematic and transfer function figure 12. type 3 schematic and transfer function gain (db) 38145 f11 0 phase C6db/oct C6db/oct gain phase (deg) freq C90 C180 C270 C360 r b v ref r1 r2 fb c2 in out + C c1 gain (db) 38145 f12 0 phase C6db/oct +6db/oct C6db/oct gain phase (deg) freq C90 C180 C270 C360 r b v ref r1 r2 fb c2 in out + C c1 c3 r3
ltc3814-5 21 38145fc if breadboard measurement is not practical, mathemat- ical software such as mathcad or matlab can be used to generate plots from the transfer function given in equation 1. a spice simulation can also be used to gener- ate approximate gain/phase curves. plug the expected capacitor, inductor and mosfet values into the following spice deck and generate an ac plot of v out /v ith with gain in db and phase in degrees. refer to your spice manual for details of how to generate this plot. *this le simulates a simpli ed model of the 3814-5 for generating a v(out)/(vith) or a v(out)/v(outin) bode plot .param vout=24 .param vin=12 .param l=10u .param cout=270u .param esr=.018 .param rload=24 * .param rdson=0.02 .param vrng=1 .param vsnsmax={0.173*vrng-0.026} .param k={vsnsmax/rdson/1.2} .param wz={1/esr/cout} .param wp={2/rload/cout} * * feedback ampli er rfb1 outin vfb 29k rfb2 vfb 0 1k eithx ithx 0 laplace {0.8-v(vfb)} = {1/(1+s/1000)} eith ith 0 value={limit(1e6*v(ithx),0,2.4)} cc1 ith vfb 100p cc2 ith x1 0.01p rc x1 vfb 100k * * modulator/output stage eout out 0 laplace {v(ith)} = {0.5*k*rload*vin/vout *(1+s/wz)/(1+s/wp) *(1-s*l/rload*vout*vout/vin/vin)} rload out 0 {rload} * vstim out outin dc=0 ac=10m; ac stimulus .ac dec 100 10 10meg .probe .end with the gain/phase plot in hand, a loop crossover fre- quency can be chosen. usually the curves look something like figure 10. choose the crossover frequency about 25% of the switching frequency for maximum bandwidth. al- though it may be tempting to go beyond f sw /4, remember that signi? cant phase shift occurs at half the switching frequency that isnt modeled in the above h(s) equation and pspice code. note the gain (gain, in db) and phase (phase, in degrees) at this point. the desired feedback ampli? er gain will be Cgain to make the loop gain at 0db at this frequency. now calculate the needed phase boost, assuming 60 as a target phase margin: boost = C (phase + 30) if the required boost is less than 60, a type 2 loop can be used successfully, saving two external components. boost values greater than 60 usually require type 3 loops for satisfactory performance. finally, choose a convenient resistor value for r1 (10k is usually a good value). now calculate the remaining values: (k is a constant used in the calculations) f = chosen crossover frequency g = 10 (gain/20) (this converts gain in db to g in absolute gain) applications information
ltc3814-5 22 38145fc type 2 loop: k = t a n boost 2 + 45 c2 = 1 2 ?f?g?k?r1 c1 = c2 k 2 1 () r2 = k 2 ?f?c1 r b = v ref (r1) v out v ref type 3 loop: k = t a n 2 boost 4 + 45 c2 = 1 2 ?f?g?r1 c1 = c2 k 1 () r2 = k 2 ?f?c1 r3 = r1 k 1 c3 = 1 2 fk? r3 r b = v ref (r1) v out v ref spice or mathematical software can be used to generate the gain/phase plots for the compensated power supply to do a sanity check on the component values before trying them out on the actual hardware. for software, use the following transfer function: t(s) = a(s)h(s) where h(s) was given in equation 2 and a(s) depends on compensation circuit used: type 2: a (s) = 1+ s?r2?c1 s?r1? c1 + c2 () ?1 + s?r2? c1? c2 c1 + c2 ? ? ? ? ? ? type 3: a (s) = 1 s?r1? c1 + c2 () ? 1+ s? r1 + r3 () ?c3 () ?1 + s?r2?c1 () 1+ s?r3?c3 () ?1 + s?r2? c1? c2 c1 + c2 ? ? ? ? ? ? for spice, simulate the previous pspice code with calculated compensation values entered and generate a gain/phase plot of v out /v outin . fault conditions: current limit the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in the ltc3814-5, the maximum sense voltage is controlled by the voltage on the v rng pin. with peak current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. the corresponding output current limit is: i limit = v sns(max) r ds(on) t ? 1 2 i l the current limit value should be checked to ensure that i limit(min) > i out(max) . the minimum value of current limit generally occurs at the lowest v in at the highest ambient temperature, conditions that cause the largest power loss in the converter. note that it is important to check for self-consistency between the assumed mosfet junction temperature and the resulting value of i limit which heats the mosfet switches. caution should be used when setting the current limit based upon the r ds(on) of the mosfets. the maximum current limit is determined by the minimum mosfet on-resistance. data sheets typically specify nominal and maximum values for r ds(on) , but not a minimum. applications information
ltc3814-5 23 38145fc a reasonable assumption is that the minimum r ds(on) lies the same percentage below the typical value as the maximum lies above it. consult the mosfet manufacturer for further guidelines. note that in a boost mode architecture, it is only possible to provide protection for soft shorts where v out > v in . for hard shorts, the inductor current is limited only by the input supply capability. run/soft-start function the run/ss pin is a multipurpose pin that provides a soft- start function and a means to shut down the ltc3814-5. soft-start reduces the input supplys surge current by controlling the ramp rate of the i th voltage, eliminates output overshoot and can also be used for power supply sequencing. pulling run/ss below 0.9v puts the ltc3814-5 into a low quiescent current shutdown (i q = 224a). this pin can be driven directly from logic as shown in figure 14. releasing the run/ss pin allows an internal 1.4a current source to charge up the soft-start capacitor, c ss . when the voltage on run/ss reaches 0.9v, the ltc3814-5 turns on and begins ramping the i th voltage at v ith = v ss C 0.9v. as the run/ss voltage increases from 0.9v to 3.3v, the current limit is increased from 0% to 100% of its maximum value. the run/ss voltage continues to charge until it reaches its internally clamped value of 4v. if run/ss starts at 0v, the delay before starting is approximately: t delay,start = 0.9v 1.4a c ss = 0.64s/f () c ss plus an additional delay, before the current limit reaches its maximum value of: t delay,reg 2.4v 1.4a c ss the start delay can be reduced by using diode d1 in figure 13. ef? ciency considerations the percent ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in ltc3814-5 circuits: 1. dc i 2 r losses. these arise from the resistances of the mosfets, inductor and pc board traces and cause the ef? ciency to drop at high input currents. the input current is maximum at maximum output current and minimum input voltage. the average input current ? ows through l, but is chopped between the top and bottom mosfets. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and the board traces to obtain the dc i 2 r loss. for example, if r ds(on) = 0.01 and r l = 0.005, the loss will range from 15mw to 1.5w as the input current varies from 1a to 10a. 2. transition loss. this loss arises from the brief amount of time the bottom mosfet spends in the saturated region during switch node transitions. it depends upon the output voltage, load current, driver strength and mosfet capacitance, among other factors. the loss is signi? cant at output voltages above 20v and can be estimated from the second term of the p main equa- tion found in the power mosfet selection section. when transition losses are signi? cant, ef? ciency can be improved by lowering the frequency and/or using a bottom mosfet(s) with lower c rss at the expense of higher r ds(on) . 3. intv cc current. this is the sum of the mosfet driver and control currents. control current is typically applications information figure 13. run/ss pin interfacing 3.3v or 5v run/ss d1 c ss 38145 f13 run/ss c ss
ltc3814-5 24 38145fc about 3ma and driver current can be calculated by: i gate = f(q g(top) + q g(bot) ), where q g(top) and q g(bot) are the gate charges of the top and bottom mosfets. this loss is proportional to the supply voltage that intv cc is derived from, i.e., v in , v out or an external supply connected to intv cc . 4. c out loss. the output capacitor has the dif? cult job of ? l tering the large rms input current out of the synchro- nous mosfet. it must have a very low esr to minimize the ac i 2 r loss . other losses, including c in esr loss, schottky diode d1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. when making adjustments to improve ef? ciency, the input cur- rent is the best indicator of changes in ef? ciency. if you make a change and the input current decreases, then the ef? ciency has increased. if there is no change in input current, then there is no change in ef? ciency. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when load step occurs, v out immediately shifts by an amount equal to ?i load (esr), where esr is the effective series resistance of c out . ?i load also begins to charge or dis- charge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. design example as a design example, take a supply with the following speci- ? cations: v in = 12v 20%, v out = 24v 5%, i out(max) = 5a, f = 250khz. since v in can vary around the 12v nominal value, connect a resistive divider from v in to v off to keep the frequency independent of v in changes: r1 r2 = 12v 1.55v ? 1= 6.74 choose r1 = 133k and r2 = 20k. now calculate timing resistor r off : r off = 1+ 133k / 20k 250khz ? 76pf = 402.6k the duty cycle is: d = 1? 12v 24v = 0.5 and the maximum input current is: i in(max) = 5a 1? 0.5 = 10a choose the inductor for about 40% ripple current at the maximum v in : l = 12v 250khz ? 0.4 ? 10a 1 12v 24v = 6 h the peak inductor current is: i l(peak) = 5a 1? 0.5 + 1 2 (4a) = 12a so, choose the cdep147 5.9h inductor with i sat = 16.4a at 100c. next, choose the bottom mosfet switch. since the drain of the mosfet will see the full output voltage plus any ringing, choose a 40v mosfet to provide a margin of safety. the si7848dp has: bv dss = 40v r ds(on) = 9m(max)/7.5m(nom), = 0.006/c, c miller = (14nc C 6nc)/20v = 400pf, v gs(miller) = 3.5v, ja = 20c/w. this yields a nominal sense voltage of: v sns(nom) = 1.7 ? 0.0075 ?5a 1? 0.5 = 128mv applications information
ltc3814-5 25 38145fc to guarantee proper current limit at worst-case conditions, increase nominal v sns by 50% to 190mv. to check if the current limit is acceptable at v sns = 190mv, assume a junction temperature of about 30c above a 70c ambient ( 100c = 1.4): i in(max) 190mv 1.4 ? 0.009 ? 1 2 ?4a = 13a i out(max) = i in(max) ? (1-d max ) = 6.5a and double-check the assumed t j in the mosfet: p top = 1 1 0.5 6.5a () 2 (1.4)(0.009 ) = 1.06w t j = 70c + 1.06w ? 20c/w = 91c verify that the si7848dp is also a good choice for the bottom mosfet by checking its power dissipation at current limit and minimum input voltage, assuming a junction temperature of 30c above a 70c ambient ( 100c = 1.4): p bot = 0.5 6.5a 1 0.5 2 (1.4) (0.009 ) + 1 2 (24v) 2 6.5a 1 0.5 (2)(400pf) ? 1 12v 3.5v + 1 3.5v (250khz) = 1.06w + 0.30w = 1.36w t j = 70c + 1.36w ? 20c/w = 97c the junction temperature will be signi? cantly less at nominal current, but this analysis shows that careful at- tention to heat sinking on the board will be necessary in this circuit. since v in is always between 4.5v and 14v, it can be con- nected directly to the intv cc and drv cc pins. c out is chosen for an rms current rating of about 5a at 85c. the output capacitors are chosen for a low esr of 0.018 to minimize output voltage changes due to inductor ripple current and load steps. the ripple voltage will be only: v out(ripple) = (5a) 1 250khz ? 330 f + 0.018 1 0.5 = 0.25v ( a bout 1%) a 0a to 5a load step will cause an output change of up to: ?v out(step) = ?i load ? esr = 5a ? 0.018 = 90mv an optional 10f ceramic output capacitor is included to minimize the effect of esl in the output ripple. the complete circuit is shown in figure 14. applications information
ltc3814-5 26 38145fc figure 14. 12v input voltage to 24v/5a pgood v off pgood v rng i th sgnd v fb sgnd pgnd pgnd run/ss i off c off 100pf c ss 1000pf v in 12v v out v out 24v 5a c c2 470pf r c 250k r fb2 1k r fb1 , 29.4k ltc3814-5 extv cc tg sw bg pgnd intv cc ndrv boost 38145 f14 c b 0.1f c drvcc 0.1f c vcc 1f r off 403k 133k d b bas19 m2 si7848dp c out1 330f 35v 2 c out2 10f 50v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c c1 47pf 20k c in1 68f 20v c in2 1f 20v m1 si7848dp l1 5.9h d1 b1100 applications information
ltc3814-5 27 38145fc pc board layout checklist when laying out a pc board follow one of two suggested approaches. the simple pc board layout requires a dedi- cated ground plane layer. also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. ? the ground plane layer should not have any traces and it should be as close as possible to the layer with power mosfets. ? place c in , c out , mosfets, d1 and inductor all in one compact area. it may help to have some components on the bottom side of the board. ? use an immediate via to connect the components to ground plane including sgnd and pgnd of ltc3814-5. use several bigger vias for power components. ? use compact plane for switch node (sw) to improve cooling of the mosfets and to keep emi down. ? use planes for v in and v out to maintain good voltage ? ltering and to keep power losses low. ? flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power component. you can connect the copper areas to any dc net (v in , v out , gnd or to any other dc rail in your system). when laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper opera- tion of the controller. ? segregate the signal and power grounds. all small signal components should return to the sgnd pin at one point which is then tied to the pgnd pin close to the source of m2. ? place m2 as close to the controller as possible, keeping the pgnd, bg and sw traces short. ? connect the input capacitor(s) c in close to the pow- er mosfets. this capacitor carries the mosfet ac current. ? keep the high dv/dt sw, boost and tg nodes away from sensitive small-signal nodes. ? connect the intv cc decoupling capacitor c vcc closely to the intv cc and sgnd pins. ? connect the top driver boost capacitor c b closely to the boost and sw pins. ? connect the bottom driver decoupling capacitor c intvcc closely to the intv cc and pgnd pins. applications information
ltc3814-5 28 38145fc package description fe16 (ba) tssop rev h 0910 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8 10 9 4.90 C 5.10* (.193 C .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 2.74 (.108) 2.74 (.108) 0.195 C 0.30 (.0077 C .0118) typ 2 millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in recommended solder pad layout 3. drawing not to scale 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.74 (.108) 2.74 (.108) see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev h) exposed pad variation ba
ltc3814-5 29 38145fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number c 01/11 updated description section changed operating junction temperature range in absolute maximum ratings and order information sections remove lead based part numbers from order information updated note 2 updated fault monitoring/protection section updated equations updated related parts 1 2 2 4 10 22 30 (revision history begins at rev c)
ltc3814-5 30 38145fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0111 rev c ? printed in usa typical application 24v input voltage to 50v/5a part number description comments ltc3786 low i q synchronous boost controller 2.5v v in 38v, v out up to 60v, fixed operating frequency 50khz to 900khz, msop-16e, 3mm 3mm qfn-16 ltc3787 2-phase, single output synchronous step-up controller 2.5v v in 38v, v out up to 60v, 50khz to 900khz, ssop-28, 4mm 5mm qfn-28 ltc3788/ltc3788-1 2-phase, dual output synchronous step-up controller 2.5v v in 38v, v out up to 60v, 50khz to 900khz, ssop-28 ltc3862/ltc3862-1 2-phase current mode step-up dc/dc controller 4v v in 36v, 5v or 10v gate drive, 75khz to 500khz ltc3813 100v maximum v out synchronous step-up dc/dc controller no r sense , large 1 gate driver, adjustable off-time, ssop-28 ltc1871, ltc1871-1, ltc1871-7 wide input range, no r sense low quiescent current flyback, boost and sepic controller adjustable switching frequency, 2.5v v in 36v, burst mode operation at light load, msop-10 lt3757 boost, flyback, sepic and inverting controller 2.9v v in 40v, 100khz to 1mhz programmable operation frequency, 3mm 3mm dfn-10 and msop-10e lt3758 boost, flyback, sepic and inverting controller 5.5v v in 100v, 100khz to 1mhz programmable operation frequency, 3mm 3mm dfn-10 and msop-10e pgood pgood v rng i th sgnd v fb sgnd pgnd pgnd run/ss i off v off c off 100pf c ss 1000pf v in 12v* to 40v *i out(max) = 2a at v in = 12v v out 50v 5a m3 zxmn10a07f c c2 330pf r c 300k r fb2 499 r fb1 30.9k ltc3814-5 extv cc tg sw bg pgnd intv cc ndrv boost 38145 ta02 c b 0.1f c drvcc 0.1f c vcc 1f 150k 100k 10k r ndrv 100k d b bas19 m2 si7850dp c out1 220f 63v 2 c out2 10f 100v 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c c1 150pf c in1 68f 50v c in2 1f 50v m1 si7850dp l1 10h d1 b1100 v out v in r off 806k 143k related parts

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